1. Field of the Invention
The present invention relates to a bus system. In particular, it is related to a bus system and a retry method capable of avoiding development of live-lock between retries when a transmission request from a master device is rejected by a slave.
2. Description of the Prior Art
FIG. 12 is a diagram of an example of a conventional bus system. A first master device including a master unit 1-1 and a master interface 91-1 and a second master device including a master unit 1-2 and a master interface 91-2 are connected to a CW bus 3 that transmits commands, addresses, write data, etc. In addition, a slave device including a slave unit 5 and a slave interface 92 is connected to the CW bus 3. Furthermore, the master interface 91-1 of the first master device, the master interface 91-2 of the second master device, and the slave interface 92 of the slave device are connected to an RD bus 6 that transmits read data.
A transmission request REQm1, command CMDm1, address ADm1, and write data WDm1 are sent from the master unit 1-1 of the first master device to the master interface 91-1. In the opposite direction—from the master interface 91-1 to the master unit 1-1—a command acknowledgement CACKm1 or bus error signal BERm1 is sent. In addition, a transmission request REQb, command CMDb, and address/write data AD/WDb are sent from the master interface 91-1 to the slave interface 92 of the slave device via the CW bus 3. In the opposite direction—from the slave interface 92 to the master interface 91-1 via the CW bus 3—an acknowledgement response ACKb or non-acknowledgement response NACKb is sent.
In the same manner, a transmission request REQm2, command CMDm2, address ADm2, and write data WDm2 are sent from the master unit 1-2 to the master interface 91-2 of the second master device. In the opposite direction—from the master interface 91-2 to the master unit 1-2—a command acknowledgement CACKm2 or bus error signal BERm2 is sent. In addition, a transmission request REQb, command CMDb, and a multiplexed address/write data AD/WDb are sent from the master interface 91-2 to the slave interface 92 of the slave device via the CW bus 3. In the opposite direction—from the slave interface 92 to the master interface 91-2 via the CW bus 3—an acknowledgement response ACKb or non-acknowledgement response NACKb is sent.
From the slave interface 92 of the slave device to the slave unit 5, a transmission request REQs, command CMDs, address ADs, and write data WDs are sent. In the opposite direction—from the slave unit 5 to the slave interface 92—a command acknowledgement CACKs is sent.
Read data is sent from the slave unit 5 to the slave interface 92 with the read data RDs. Read data RDb is sent from the slave interface 92 to the master interface 91-1 of the first master device or the master interface 91-2 of the second master device via the RD bus 6. In the first master device, read data RDm1 is sent from the master interface 91-1 to the master unit 1-1; and in the second master device, read data RDm2 is sent from the master interface 91-2 to the master unit 1-2.
An arbitration circuit 7 is provided to decide usage rights (access) for the CW bus 3. A bus access request AREQm1 is sent from the master interface 91-1 of the first master device to the arbitration circuit 7, and a bus access request AREQm2 is sent from the master interface 91-2 of the second master device to the arbitration circuit 7. If the arbitration circuit 7 is to give bus access for the CW bus 3 to the first master device, it sends a grant signal AGNTm1 to the master interface 91-1. If the arbitration circuit 7 is to give bus access for the CW bus 3 to the second master device, it sends a grant signal AGNTm2 to the master interface 91-2.
FIG. 13 is a partial internal block diagram relating to the CW bus 3 of the master interface 91. In FIG. 13, the portion relating to the RD bus 6, more specifically the portion relating to the reception of read data, is omitted. A master protocol control circuit 11 receives transmission requests and commands from the master unit 1 and controls communication between the master unit 1 and the slave device based on protocol. A preset retry interval value RIN is stored in a retry interval value register 12. Once a non-acknowledgement response NACKb is received the counter value is reset and then the retry interval counter 13 keeps track of the number of clock pulses by incrementing the counter value each time a pulse of the clock CLK is input. The comparator 14 detects if the count value of the retry interval counter 13 matches the retry interval value RIN and makes the retry time alert signal RT to be active level. A permissible retry count PRC is stored beforehand in a retry attempt register 15. After resetting the count value as a result of the transmission request REQm from the master unit 1, a retry attempt counter 16 increments the count value every time a non-acknowledgement response NACKb is received. Once the comparator 17 detects that the count value has become a value greater than the permissible retry count PRC in the retry attempt register 15, it makes the overflow signal OF active level. In the case where the retry request circuit 18 detects that the retry time alert signal RT has changed to the active level when the overflow signal OF is at the inactive level, a retry activation request signal RRQ is sent to the master protocol control circuit 11. When the retry activation request signal RRQ is received, the master protocol control circuit 11 resends the transmission request REQb, command CMDb, and address (the address portion of the AD/WD). A bus error determination circuit 19 detects that the overflow signal OF has changed to the active level and outputs a bus error signal BERm.
FIG. 14(a) is an operation sequence chart for the conventional bus system shown in FIG. 12 and FIG. 13. The operation carried out when two master devices send out successive read transmission requests to a single slave device is illustrated in FIG. 14(a), which is referenced to describe the operation of the conventional bus system of FIG. 12.
At time point T11, a transmission request REQm1 is sent from the master unit 1-1 to the master interface 91-1. At the same time, the address ADm1, command CMDm1, etc. are simultaneously delivered to the master interface 91-1.
The master interface 91-1 makes a request for CW bus 3 bus access to the arbitration circuit 7, and if bus access is granted and the CW bus 3 is not in use, the transmission request REQb is sent out over the CW bus 3. The retry attempt counter 16 within the master interface 91-1 is reset to zero.
The slave interface 92 receives the transmission request REQb, address write data AD/WDb, and command CMDb from the master unit 1-1 via the CW bus 3, and in accordance with the received command CMDb and the status of the slave unit 5, it is determined whether to receive that transmission request REQb or reject it. As the slave unit 5 is in a reception ready state, the slave interface 92 outputs the acknowledgement response ACKb and also transmits a transmission request REQs to the slave unit 5.
Upon receiving the acknowledgement response ACKb, the master interface 91-1 sends a command acknowledgement CACKm1 to the master unit 1-1. At the same time, data phase transmission commences. With the data phase, in the case where there is a write-operation, the master interface 91-1 makes a request for write data to the master unit 1-1 and outputs the received data to the CW bus 3, however, this case is read-operation, so the master interface releases the CW bus 3 and waits a predetermined length of time until the read data is prepared.
Meanwhile, at time point T12, it is assumed that a transmission request REQm2 is sent from the master unit 1-2 to the master interface 91-2. At the same time, the address ADm2, command CMDm2, etc. are delivered to the master interface 91-2.
The master interface 91-2 makes a request for CW bus 3 bus access to the arbitration circuit 7, waits until it is accessible since it is in use, and then once bus access is granted, sends the transmission request REQb over the CW bus 3. The retry attempt counter 16 of the master interface 91-2 is reset to zero.
The slave interface 92 receives the transmission request REQb, address ADb, and command CMDb from the master unit 1-2 via the CW bus 3. Nevertheless, since the slave unit 5 is busy with processing the transmission request from the master unit 1-2, the slave interface 92 decides to reject the transmission request REQb and returns a non-acknowledgement response NACKb.
The master interface 91-2, after opening of the CW bus 3 upon reception of the non-acknowledgement response NACKb, releases the CW bus 3 and then increments the count value of the retry attempt counter 16 and determines whether or not it is greater than the permissible retry count PRC stored in the retry attempt register 15. In the case where the count value has exceeded the permissible retry count PRC, the bus error determination circuit 19 outputs the bus error signal BERm1. However, in the case of FIG. 14(a), as the count value is smaller than the permissible retry count PRC, the master interface 91-2 waits merely the length of time (the retry interval time) Tri until the retry interval counter 13 has counted a number of clock pulses equivalent to the retry interval value RIN stored in the retry interval value register 12.
Once the transmission preparation of the read data corresponding to the transmission request from the master interface 1-1 is completed, the slave interface 92 receives the read data RDs from the slave unit 5 and outputs the read data RDb to the RD bus 6.
The master interface 91-1 receives the read data RDb via the RD bus 6 and transmits the read data RDm1 to the master unit 1-1. At time point T13, the master unit 1-1 receives read data RDm1 and finishes processing of the read transmission request from the master unit 1-1.
Meanwhile, with the master interface 1-2, when the count value of the retry interval counter 13 reaches retry interval value RIN, the protocol control circuit 11 again makes a request for CW bus 3 bus access to the arbitration circuit 7. Once bus access is granted, the transmission request REQb is output over the bus.
The slave interface 92 receives the transmission request REQb, address ADb, and command CMDb from the master unit 1-2 via the CW bus 3, and as the slave unit 5 is reception ready this time, the slave interface 92 outputs an acknowledgement response ACKb over the CW bus 3 and also sends out a transmission request REQs to the slave unit 5.
Upon receiving the acknowledgement response ACKb, the master interface 91-2 sends a command acknowledgement CACKm2 to the master unit 1-2, releases the CW bus 3, and waits a predetermined length of time until the read data is prepared. Once the transmission preparation of the read data corresponding to the transmission request from the master interface 1-2 is completed, the slave interface 92 receives the read data RDs from the slave unit 5 and outputs the read data RDb to the RD bus 6. The master interface 91-2 receives the read data RDb via the RD bus 6 and transmits the read data RDm2 to the master unit 1-2. At time point T14, the master unit 1-2 receives read data RDm2 and finishes processing of the read transmission request from the master unit 1-2.
The timing chart of FIG. 14(b) illustrates the operation described above using FIG. 14(a) in a timing chart. In FIG. 14(b), there is shown the bus access request AREQm1 to the arbitration circuit 7 from the master interface 91-1 and the corresponding grant signal AGNTm1 that grants bus access to the master interface 91-1 from the arbitration circuit 7, as well as the bus access request AREQm2 to the arbitration circuit 7 from the master interface 91-2 and the corresponding grant signal AGNTm2 that grants bus access to the master interface 91-2 from the arbitration circuit 7.
With the conventional bus system, as shown here, even when transmission requests from a plurality of master units to one slave unit converge, coordination of and response to a plurality of transmission requests is possible.
Nevertheless, for example as shown in FIG. 12, in the case where the transmission request ACKb from the master unit 1-1 to the slave unit 5 periodically occurs and this matches the period of the transmission request ACKb generated based on the retry interval value RIN from the master unit 1-2, the situation where the transmission request from the master unit, 1-2 is continually rejected and not executed may continue. This is called live-lock, and since it causes a remarkable drop in bus transmission efficiency, is necessary to prevent its occurrence before it happens and if it does happen, expeditiously resolve it.
FIG. 15 is an operational sequence chart illustrating an incidence of live-lock. At time point T1, the transmission request REQm1 is transmitted from the master unit 1-1, and at time point T2, the transmission request REQm2 is transmitted from the master unit 1-2, however, since the transmission request first sent from the master unit 1-1 is received and the slave unit 5 becomes busy, the transmission request from the master unit 1-2 is rejected at the slave interface 92 and the non-acknowledgement response NACKb is returned to the master interface 91-2. The slave interface 92 begins clocking the retry interval time Tri after receiving the non-acknowledgement response NACKb.
Meanwhile, the read data RDm1 corresponding to the transmission request of the master unit 1-1 is transmitted at time point T3 from the slave unit 5 to the master unit 1-1 via the RD bus 6 and the read processing is completed. Immediately afterwards, the master unit 1-1 transmits the next transmission request REQm1. Accordingly, the transmission request from the master unit 1-1 is received and the slave unit 5 becomes busy again.
The master interface 91-2 detects that the retry interval time Tri has passed and then resends the transmission request REQb to the slave interface 92, however, as the slave unit 5 is busy it is rejected and the non-acknowledgement response NACKb is again returned to the master interface 91-2. The master interface 91-2 again begins clocking the retry interval time Tri after receiving the non-acknowledgement response NACKb.
In the case of FIG. 15, since the send period of the transmission request from the master unit 1-1 matches the resend period of the transmission request from the master interface 91-2, from this point forward only the transmission request from the master unit 1-1 continues to be executed. As the rejection of the transmission request from the master unit 1-2 continues, it becomes live-lock.
In the case where live-lock develops, in order to resolve it, either the transmission requests of the master device that is periodically sending transmission requests (in FIG. 15, the master unit 1-1) must be temporarily halted, or the master device that is experiencing live-lock (in FIG. 15, the master interface 91-2) must change the length of the retry interval time between transmission request resend attempts.
A method of temporarily halting the master device making the periodic transmission requests is disclosed in Japanese Patent Application Laid-open No. 2000-315188, wherein there is a technique that monitors bus transactions and performs control so as to cause the master device experiencing live-lock to use the bus exclusively once live-lock has developed. While use of this technique makes it possible to reliably resolve live-lock, since it is necessary to provide a live-lock detection circuit in each corresponding master device in order to detect whether a live-lock situation exists in the bus access arbitration circuit and also provide a circuit that sets exclusive bus usage for the master device that has detected a live-lock situation, the amount of hardware increases dramatically for the bus access arbitration circuit.
As for changing the length of the retry interval time for a master device experiencing live-lock, Japanese Patent Application Laid-open No. Hei 9-114750 discloses a technique whereby a plurality of retry interval time registers is provided in a master device. Then in the case where the non-acknowledgement response is consecutively received a predetermined number of times while set to the retry interval time of a first register, it is switched to a differing retry interval time of a second register. If even with this the non-acknowledgement response is received a predetermined number of times, it is subsequently switched to a different retry interval time of a third register. However, in the case where the bus is connected to a plurality of slave devices, the amount of time needed for slave device reading/writing differs drastically depending on slave device functionality such as whether a slave device has high-speed memory or low-speed peripheral devices. As a result, the appropriate retry interval time also differs for each slave device for which a transmission request may be sent. Accordingly, when a plurality of slave devices are connected to a bus, within each master device, not only must a register group that includes a plurality of registers be given for each individual slave device, but also a plurality of register groups must be provided corresponding to the plurality of slave devices, which dramatically increases the amount of hardware for the master devices.
In Japanese Patent Application Laid-open No. 2000-250850, a technique is disclosed whereby a first timetable stored with a primary retry interval time and a second timetable stored with a shorter interval time are provided to give the retry interval times for the slave device. When the first non-acknowledgement response is returned, the master device is notified of the retry interval time of the first timetable, and then upon return of the second and subsequent non-acknowledgement responses, the master device is notified of the retry interval time of the second timetable. After receiving the first non-acknowledgement response, the master device waits until the primary retry interval time of the first timetable has passed and then resends the transmission request; then after receiving the second and subsequent non-acknowledgement responses, it waits until the retry interval time of the second timetable has passed to resend the transmission request. With this technique, since the slave device is stored with a unique primary retry interval time, it is not necessary to store retry interval times that are adapted to the respective slave devices on the master side, and is thus an improvement over the technique disclosed in Japanese Patent Laid-open Hei 9-114750. However, there is still a possibility that the retry interval time of the second timetable will match the period of a transmission request from another master device causing live-lock to develop, and once in a live-lock situation, it may not be easily resolved. Nevertheless, with this technique, since substantially exclusive rights may be obtained if the retry interval time of the second timetable is set extremely short, processing of the transmission request from a master device that has received a non-acknowledgement response two or more times can be given priority and it is possible to prevent development of live-lock. However, when the slave device sent the transmission request is a device for which reading/writing takes time such as with a peripheral device, since the bus is monopolized through this technique, transmission between other master devices and slave devices connected to the bus may be halted for a long time, causing bus usage efficiency to drop.